Macros
#define	OV9655_REG_GAIN 0x00

#define	OV9655_REG_BLUE 0x01

#define	OV9655_REG_RED 0x02

#define	OV9655_REG_VREF 0x03

#define	OV9655_REG_COM1 0x04

#define	OV9655_REG_BAVE 0x05

#define	OV9655_REG_GbAVE 0x06

#define	OV9655_REG_GrAVE 0x07

#define	OV9655_REG_RAVE 0x08

#define	OV9655_REG_COM2 0x09

#define	OV9655_REG_PID 0x0A

#define	OV9655_REG_VER 0x0B

#define	OV9655_REG_COM3 0x0C

#define	OV9655_REG_COM4 0x0D

#define	OV9655_REG_COM5 0x0E

#define	OV9655_REG_COM6 0x0F

#define	OV9655_REG_AEC 0x10

#define	OV9655_REG_CLKRC 0x11

#define	OV9655_REG_COM7 0x12

#define	OV9655_REG_COM8 0x13

#define	OV9655_REG_COM9 0x14

#define	OV9655_REG_COM10 0x15

#define	OV9655_REG_REG16 0x16

#define	OV9655_REG_HSTART 0x17

#define	OV9655_REG_HSTOP 0x18

#define	OV9655_REG_VSTART 0x19

#define	OV9655_REG_VSTOP 0x1A

#define	OV9655_REG_PSHFT 0x1B

#define	OV9655_REG_MIDH 0x1C

#define	OV9655_REG_MIDL 0x1D

#define	OV9655_REG_MVFP 0x1E

#define	OV9655_REG_BOS 0x20

#define	OV9655_REG_GBOS 0x21

#define	OV9655_REG_GROS 0x22

#define	OV9655_REG_ROS 0x23

#define	OV9655_REG_AEW 0x24

#define	OV9655_REG_AEB 0x25

#define	OV9655_REG_VPT 0x26

#define	OV9655_REG_BBIAS 0x27

#define	OV9655_REG_GbBIAS 0x28

#define	OV9655_REG_PREGAIN 0x29

#define	OV9655_REG_EXHCH 0x2A

#define	OV9655_REG_EXHCL 0x2B

#define	OV9655_REG_RBIAS 0x2C

#define	OV9655_REG_ADVFL 0x2D

#define	OV9655_REG_ADVFH 0x2E

#define	OV9655_REG_YAVE 0x2F

#define	OV9655_REG_HSYST 0x30

#define	OV9655_REG_HSYEN 0x31

#define	OV9655_REG_HREF 0x32

#define	OV9655_REG_CHLF 0x33

#define	OV9655_REG_AREF1 0x34

#define	OV9655_REG_AREF2 0x35

#define	OV9655_REG_AREF3 0x36

#define	OV9655_REG_ADC1 0x37

#define	OV9655_REG_ADC2 0x38

#define	OV9655_REG_AREF4 0x39

#define	OV9655_REG_TSLB 0x3A

#define	OV9655_REG_COM11 0x3B

#define	OV9655_REG_COM12 0x3C

#define	OV9655_REG_COM13 0x3D

#define	OV9655_REG_COM14 0x3E

#define	OV9655_REG_EDGE 0x3F

#define	OV9655_REG_COM15 0x40

#define	OV9655_REG_COM16 0x41

#define	OV9655_REG_COM17 0x42

#define	OV9655_REG_MTX1 0x4F

#define	OV9655_REG_MTX2 0x50

#define	OV9655_REG_MTX3 0x51

#define	OV9655_REG_MTX4 0x52

#define	OV9655_REG_MTX5 0x53

#define	OV9655_REG_MTX6 0x54

#define	OV9655_REG_BRTN 0x55

#define	OV9655_REG_CNST1 0x56

#define	OV9655_REG_CNST2 0x57

#define	OV9655_REG_MTXS 0x58

#define	OV9655_REG_AWBOP1 0x59

#define	OV9655_REG_AWBOP2 0x5A

#define	OV9655_REG_AWBOP3 0x5B

#define	OV9655_REG_AWBOP4 0x5C

#define	OV9655_REG_AWBOP5 0x5D

#define	OV9655_REG_AWBOP6 0x5E

#define	OV9655_REG_BLMT 0x5F

#define	OV9655_REG_RLMT 0x60

#define	OV9655_REG_GLMT 0x61

#define	OV9655_REG_LCC1 0x62

#define	OV9655_REG_LCC2 0x63

#define	OV9655_REG_LCC3 0x64

#define	OV9655_REG_LCC4 0x65

#define	OV9655_REG_MANU 0x66

#define	OV9655_REG_MANV 0x67

#define	OV9655_REG_MANY 0x68

#define	OV9655_REG_VARO 0x69

#define	OV9655_REG_BD50MAX 0x6A

#define	OV9655_REG_DBLV 0x6B

#define	OV9655_REG_DNSTH 0x70

#define	OV9655_REG_POIDX 0x72

#define	OV9655_REG_PCKDV 0x73

#define	OV9655_REG_XINDX 0x74

#define	OV9655_REG_YINDX 0x75

#define	OV9655_REG_SLOP 0x7A

#define	OV9655_REG_GAM1 0x7B

#define	OV9655_REG_GAM2 0x7C

#define	OV9655_REG_GAM3 0x7D

#define	OV9655_REG_GAM4 0x7E

#define	OV9655_REG_GAM5 0x7F

#define	OV9655_REG_GAM6 0x80

#define	OV9655_REG_GAM7 0x81

#define	OV9655_REG_GAM8 0x82

#define	OV9655_REG_GAM9 0x83

#define	OV9655_REG_GAM10 0x84

#define	OV9655_REG_GAM11 0x85

#define	OV9655_REG_GAM12 0x86

#define	OV9655_REG_GAM13 0x87

#define	OV9655_REG_GAM14 0x88

#define	OV9655_REG_GAM15 0x89

#define	OV9655_REG_COM18 0x8B

#define	OV9655_REG_COM19 0x8C

#define	OV9655_REG_COM20 0x8D

#define	OV9655_REG_DMLNL 0x92

#define	OV9655_REG_DMLNH 0x93

#define	OV9655_REG_LCC6 0x9D

#define	OV9655_REG_LCC7 0x9E

#define	OV9655_REG_AECH 0xA1

#define	OV9655_REG_BD50 0xA2

#define	OV9655_REG_BD60 0xA3

#define	OV9655_REG_COM21 0xA4

#define	OV9655_REG_GREEN 0xA6

#define	OV9655_REG_VZST 0xA7

#define	OV9655_REG_REFA8 0xA8

#define	OV9655_REG_REFA9 0xA9

#define	OV9655_REG_BLC1 0xAC

#define	OV9655_REG_BLC2 0xAD

#define	OV9655_REG_BLC3 0xAE

#define	OV9655_REG_BLC4 0xAF

#define	OV9655_REG_BLC5 0xB0

#define	OV9655_REG_BLC6 0xB1

#define	OV9655_REG_BLC7 0xB2

#define	OV9655_REG_BLC8 0xB3

#define	OV9655_REG_CTRLB4 0xB4

#define	OV9655_REG_FRSTL 0xB7

#define	OV9655_REG_FRSTH 0xB8

#define	OV9655_REG_ADBOFF 0xBC

#define	OV9655_REG_ADROFF 0xBD

#define	OV9655_REG_ADGbOFF 0xBE

#define	OV9655_REG_ADGrOFF 0xBF

#define	OV9655_REG_COM23 0xC4

#define	OV9655_REG_BD60MAX 0xC5

#define	OV9655_REG_COM24 0xC7

#define	CCIR656_FORMAT 0x40

#define	HREF_SKIP_0 0x00

#define	HREF_SKIP_1 0x04

#define	HREF_SKIP_3 0x08

#define	SOFT_SLEEP_MODE 0x10

#define	ODCAP_1x 0x00

#define	ODCAP_2x 0x01

#define	ODCAP_3x 0x02

#define	ODCAP_4x 0x03

#define	COLOR_BAR_OUTPUT 0x80

#define	OUTPUT_MSB_LAS_SWAP 0x40

#define	PIN_REMAP_RESETB_EXPST 0x08

#define	RGB565_FORMAT 0x00

#define	RGB_OUTPUT_AVERAGE 0x04

#define	SINGLE_FRAME 0x01

#define	SLAM_MODE_ENABLE 0x40

#define	EXPOSURE_NORMAL_MODE 0x01

#define	SCCB_REG_RESET 0x80

#define	FORMAT_CTRL_15fpsVGA 0x00

#define	FORMAT_CTRL_30fpsVGA_NoVArioPixel 0x50

#define	FORMAT_CTRL_30fpsVGA_VArioPixel 0x60

#define	OUTPUT_FORMAT_RAWRGB 0x00

#define	OUTPUT_FORMAT_RAWRGB_DATA 0x00

#define	OUTPUT_FORMAT_RAWRGB_INTERP 0x01

#define	OUTPUT_FORMAT_YUV 0x02

#define	OUTPUT_FORMAT_RGB 0x03

#define	GAIN_2x 0x00

#define	GAIN_4x 0x10

#define	GAIN_8x 0x20

#define	GAIN_16x 0x30

#define	GAIN_32x 0x40

#define	GAIN_64x 0x50

#define	GAIN_128x 0x60

#define	DROP_VSYNC 0x04

#define	DROP_HREF 0x02

#define	RESETb_REMAP_SLHS 0x80

#define	HREF_CHANGE_HSYNC 0x40

#define	PCLK_ON 0x00

#define	PCLK_OFF 0x20

#define	PCLK_POLARITY_REV 0x10

#define	HREF_POLARITY_REV 0x08

#define	RESET_ENDPOINT 0x04

#define	VSYNC_NEG 0x02

#define	HSYNC_NEG 0x01

#define	PCLK_DELAY_0 0x00

#define	PCLK_DELAY_2 0x40

#define	PCLK_DELAY_4 0x80

#define	PCLK_DELAY_6 0xC0

#define	OUTPUT_BITWISE_REV 0x20

#define	UV_NORMAL 0x00

#define	UV_FIXED 0x10

#define	YUV_SEQ_YUYV 0x00

#define	YUV_SEQ_YVYU 0x02

#define	YUV_SEQ_VYUY 0x04

#define	YUV_SEQ_UYVY 0x06

#define	BANDING_FREQ_50 0x02

#define	RGB_NORMAL 0x00

#define	RGB_565 0x10

#define	RGB_555 0x30

Macro Definition Documentation

◆ BANDING_FREQ_50

#define BANDING_FREQ_50 0x02

◆ CCIR656_FORMAT

#define CCIR656_FORMAT 0x40

◆ COLOR_BAR_OUTPUT

#define COLOR_BAR_OUTPUT 0x80

◆ DROP_HREF

#define DROP_HREF 0x02

◆ DROP_VSYNC

#define DROP_VSYNC 0x04

◆ EXPOSURE_NORMAL_MODE

#define EXPOSURE_NORMAL_MODE 0x01

◆ FORMAT_CTRL_15fpsVGA

#define FORMAT_CTRL_15fpsVGA 0x00

◆ FORMAT_CTRL_30fpsVGA_NoVArioPixel

#define FORMAT_CTRL_30fpsVGA_NoVArioPixel 0x50

◆ FORMAT_CTRL_30fpsVGA_VArioPixel

#define FORMAT_CTRL_30fpsVGA_VArioPixel 0x60

◆ GAIN_128x

#define GAIN_128x 0x60

◆ GAIN_16x

#define GAIN_16x 0x30

◆ GAIN_2x

#define GAIN_2x 0x00

◆ GAIN_32x

#define GAIN_32x 0x40

◆ GAIN_4x

#define GAIN_4x 0x10

◆ GAIN_64x

#define GAIN_64x 0x50

◆ GAIN_8x

#define GAIN_8x 0x20

◆ HREF_CHANGE_HSYNC

#define HREF_CHANGE_HSYNC 0x40

◆ HREF_POLARITY_REV

#define HREF_POLARITY_REV 0x08

◆ HREF_SKIP_0

#define HREF_SKIP_0 0x00

◆ HREF_SKIP_1

#define HREF_SKIP_1 0x04

◆ HREF_SKIP_3

#define HREF_SKIP_3 0x08

◆ HSYNC_NEG

#define HSYNC_NEG 0x01

◆ ODCAP_1x

#define ODCAP_1x 0x00

◆ ODCAP_2x

#define ODCAP_2x 0x01

◆ ODCAP_3x

#define ODCAP_3x 0x02

◆ ODCAP_4x

#define ODCAP_4x 0x03

◆ OUTPUT_BITWISE_REV

#define OUTPUT_BITWISE_REV 0x20

◆ OUTPUT_FORMAT_RAWRGB

#define OUTPUT_FORMAT_RAWRGB 0x00

◆ OUTPUT_FORMAT_RAWRGB_DATA

#define OUTPUT_FORMAT_RAWRGB_DATA 0x00

◆ OUTPUT_FORMAT_RAWRGB_INTERP

#define OUTPUT_FORMAT_RAWRGB_INTERP 0x01

◆ OUTPUT_FORMAT_RGB

#define OUTPUT_FORMAT_RGB 0x03

◆ OUTPUT_FORMAT_YUV

#define OUTPUT_FORMAT_YUV 0x02

◆ OUTPUT_MSB_LAS_SWAP

#define OUTPUT_MSB_LAS_SWAP 0x40

◆ OV9655_REG_ADBOFF

#define OV9655_REG_ADBOFF 0xBC

◆ OV9655_REG_ADC1

#define OV9655_REG_ADC1 0x37

◆ OV9655_REG_ADC2

#define OV9655_REG_ADC2 0x38

◆ OV9655_REG_ADGbOFF

#define OV9655_REG_ADGbOFF 0xBE

◆ OV9655_REG_ADGrOFF

#define OV9655_REG_ADGrOFF 0xBF

◆ OV9655_REG_ADROFF

#define OV9655_REG_ADROFF 0xBD

◆ OV9655_REG_ADVFH

#define OV9655_REG_ADVFH 0x2E

◆ OV9655_REG_ADVFL

#define OV9655_REG_ADVFL 0x2D

◆ OV9655_REG_AEB

#define OV9655_REG_AEB 0x25

◆ OV9655_REG_AEC

#define OV9655_REG_AEC 0x10

◆ OV9655_REG_AECH

#define OV9655_REG_AECH 0xA1

◆ OV9655_REG_AEW

#define OV9655_REG_AEW 0x24

◆ OV9655_REG_AREF1

#define OV9655_REG_AREF1 0x34

◆ OV9655_REG_AREF2

#define OV9655_REG_AREF2 0x35

◆ OV9655_REG_AREF3

#define OV9655_REG_AREF3 0x36

◆ OV9655_REG_AREF4

#define OV9655_REG_AREF4 0x39

◆ OV9655_REG_AWBOP1

#define OV9655_REG_AWBOP1 0x59

◆ OV9655_REG_AWBOP2

#define OV9655_REG_AWBOP2 0x5A

◆ OV9655_REG_AWBOP3

#define OV9655_REG_AWBOP3 0x5B

◆ OV9655_REG_AWBOP4

#define OV9655_REG_AWBOP4 0x5C

◆ OV9655_REG_AWBOP5

#define OV9655_REG_AWBOP5 0x5D

◆ OV9655_REG_AWBOP6

#define OV9655_REG_AWBOP6 0x5E

◆ OV9655_REG_BAVE

#define OV9655_REG_BAVE 0x05

◆ OV9655_REG_BBIAS

#define OV9655_REG_BBIAS 0x27

◆ OV9655_REG_BD50

#define OV9655_REG_BD50 0xA2

◆ OV9655_REG_BD50MAX

#define OV9655_REG_BD50MAX 0x6A

◆ OV9655_REG_BD60

#define OV9655_REG_BD60 0xA3

◆ OV9655_REG_BD60MAX

#define OV9655_REG_BD60MAX 0xC5

◆ OV9655_REG_BLC1

#define OV9655_REG_BLC1 0xAC

◆ OV9655_REG_BLC2

#define OV9655_REG_BLC2 0xAD

◆ OV9655_REG_BLC3

#define OV9655_REG_BLC3 0xAE

◆ OV9655_REG_BLC4

#define OV9655_REG_BLC4 0xAF

◆ OV9655_REG_BLC5

#define OV9655_REG_BLC5 0xB0

◆ OV9655_REG_BLC6

#define OV9655_REG_BLC6 0xB1

◆ OV9655_REG_BLC7

#define OV9655_REG_BLC7 0xB2

◆ OV9655_REG_BLC8

#define OV9655_REG_BLC8 0xB3

◆ OV9655_REG_BLMT

#define OV9655_REG_BLMT 0x5F

◆ OV9655_REG_BLUE

#define OV9655_REG_BLUE 0x01

◆ OV9655_REG_BOS

#define OV9655_REG_BOS 0x20

◆ OV9655_REG_BRTN

#define OV9655_REG_BRTN 0x55

◆ OV9655_REG_CHLF

#define OV9655_REG_CHLF 0x33

◆ OV9655_REG_CLKRC

#define OV9655_REG_CLKRC 0x11

◆ OV9655_REG_CNST1

#define OV9655_REG_CNST1 0x56

◆ OV9655_REG_CNST2

#define OV9655_REG_CNST2 0x57

◆ OV9655_REG_COM1

#define OV9655_REG_COM1 0x04

◆ OV9655_REG_COM10

#define OV9655_REG_COM10 0x15

◆ OV9655_REG_COM11

#define OV9655_REG_COM11 0x3B

◆ OV9655_REG_COM12

#define OV9655_REG_COM12 0x3C

◆ OV9655_REG_COM13

#define OV9655_REG_COM13 0x3D

◆ OV9655_REG_COM14

#define OV9655_REG_COM14 0x3E

◆ OV9655_REG_COM15

#define OV9655_REG_COM15 0x40

◆ OV9655_REG_COM16

#define OV9655_REG_COM16 0x41

◆ OV9655_REG_COM17

#define OV9655_REG_COM17 0x42

◆ OV9655_REG_COM18

#define OV9655_REG_COM18 0x8B

◆ OV9655_REG_COM19

#define OV9655_REG_COM19 0x8C

◆ OV9655_REG_COM2

#define OV9655_REG_COM2 0x09

◆ OV9655_REG_COM20

#define OV9655_REG_COM20 0x8D

◆ OV9655_REG_COM21

#define OV9655_REG_COM21 0xA4

◆ OV9655_REG_COM23

#define OV9655_REG_COM23 0xC4

◆ OV9655_REG_COM24

#define OV9655_REG_COM24 0xC7

◆ OV9655_REG_COM3

#define OV9655_REG_COM3 0x0C

◆ OV9655_REG_COM4

#define OV9655_REG_COM4 0x0D

◆ OV9655_REG_COM5

#define OV9655_REG_COM5 0x0E

◆ OV9655_REG_COM6

#define OV9655_REG_COM6 0x0F

◆ OV9655_REG_COM7

#define OV9655_REG_COM7 0x12

◆ OV9655_REG_COM8

#define OV9655_REG_COM8 0x13

◆ OV9655_REG_COM9

#define OV9655_REG_COM9 0x14

◆ OV9655_REG_CTRLB4

#define OV9655_REG_CTRLB4 0xB4

◆ OV9655_REG_DBLV

#define OV9655_REG_DBLV 0x6B

◆ OV9655_REG_DMLNH

#define OV9655_REG_DMLNH 0x93

◆ OV9655_REG_DMLNL

#define OV9655_REG_DMLNL 0x92

◆ OV9655_REG_DNSTH

#define OV9655_REG_DNSTH 0x70

◆ OV9655_REG_EDGE

#define OV9655_REG_EDGE 0x3F

◆ OV9655_REG_EXHCH

#define OV9655_REG_EXHCH 0x2A

◆ OV9655_REG_EXHCL

#define OV9655_REG_EXHCL 0x2B

◆ OV9655_REG_FRSTH

#define OV9655_REG_FRSTH 0xB8

◆ OV9655_REG_FRSTL

#define OV9655_REG_FRSTL 0xB7

◆ OV9655_REG_GAIN

#define OV9655_REG_GAIN 0x00

◆ OV9655_REG_GAM1

#define OV9655_REG_GAM1 0x7B

◆ OV9655_REG_GAM10

#define OV9655_REG_GAM10 0x84

◆ OV9655_REG_GAM11

#define OV9655_REG_GAM11 0x85

◆ OV9655_REG_GAM12

#define OV9655_REG_GAM12 0x86

◆ OV9655_REG_GAM13

#define OV9655_REG_GAM13 0x87

◆ OV9655_REG_GAM14

#define OV9655_REG_GAM14 0x88

◆ OV9655_REG_GAM15

#define OV9655_REG_GAM15 0x89

◆ OV9655_REG_GAM2

#define OV9655_REG_GAM2 0x7C

◆ OV9655_REG_GAM3

#define OV9655_REG_GAM3 0x7D

◆ OV9655_REG_GAM4

#define OV9655_REG_GAM4 0x7E

◆ OV9655_REG_GAM5

#define OV9655_REG_GAM5 0x7F

◆ OV9655_REG_GAM6

#define OV9655_REG_GAM6 0x80

◆ OV9655_REG_GAM7

#define OV9655_REG_GAM7 0x81

◆ OV9655_REG_GAM8

#define OV9655_REG_GAM8 0x82

◆ OV9655_REG_GAM9

#define OV9655_REG_GAM9 0x83

◆ OV9655_REG_GbAVE

#define OV9655_REG_GbAVE 0x06

◆ OV9655_REG_GbBIAS

#define OV9655_REG_GbBIAS 0x28

◆ OV9655_REG_GBOS

#define OV9655_REG_GBOS 0x21

◆ OV9655_REG_GLMT

#define OV9655_REG_GLMT 0x61

◆ OV9655_REG_GrAVE

#define OV9655_REG_GrAVE 0x07

◆ OV9655_REG_GREEN

#define OV9655_REG_GREEN 0xA6

◆ OV9655_REG_GROS

#define OV9655_REG_GROS 0x22

◆ OV9655_REG_HREF

#define OV9655_REG_HREF 0x32

◆ OV9655_REG_HSTART

#define OV9655_REG_HSTART 0x17

◆ OV9655_REG_HSTOP

#define OV9655_REG_HSTOP 0x18

◆ OV9655_REG_HSYEN

#define OV9655_REG_HSYEN 0x31

◆ OV9655_REG_HSYST

#define OV9655_REG_HSYST 0x30

◆ OV9655_REG_LCC1

#define OV9655_REG_LCC1 0x62

◆ OV9655_REG_LCC2

#define OV9655_REG_LCC2 0x63

◆ OV9655_REG_LCC3

#define OV9655_REG_LCC3 0x64

◆ OV9655_REG_LCC4

#define OV9655_REG_LCC4 0x65

◆ OV9655_REG_LCC6

#define OV9655_REG_LCC6 0x9D

◆ OV9655_REG_LCC7

#define OV9655_REG_LCC7 0x9E

◆ OV9655_REG_MANU

#define OV9655_REG_MANU 0x66

◆ OV9655_REG_MANV

#define OV9655_REG_MANV 0x67

◆ OV9655_REG_MANY

#define OV9655_REG_MANY 0x68

◆ OV9655_REG_MIDH

#define OV9655_REG_MIDH 0x1C

◆ OV9655_REG_MIDL

#define OV9655_REG_MIDL 0x1D

◆ OV9655_REG_MTX1

#define OV9655_REG_MTX1 0x4F

◆ OV9655_REG_MTX2

#define OV9655_REG_MTX2 0x50

◆ OV9655_REG_MTX3

#define OV9655_REG_MTX3 0x51

◆ OV9655_REG_MTX4

#define OV9655_REG_MTX4 0x52

◆ OV9655_REG_MTX5

#define OV9655_REG_MTX5 0x53

◆ OV9655_REG_MTX6

#define OV9655_REG_MTX6 0x54

◆ OV9655_REG_MTXS

#define OV9655_REG_MTXS 0x58

◆ OV9655_REG_MVFP

#define OV9655_REG_MVFP 0x1E

◆ OV9655_REG_PCKDV

#define OV9655_REG_PCKDV 0x73

◆ OV9655_REG_PID

#define OV9655_REG_PID 0x0A

◆ OV9655_REG_POIDX

#define OV9655_REG_POIDX 0x72

◆ OV9655_REG_PREGAIN

#define OV9655_REG_PREGAIN 0x29

◆ OV9655_REG_PSHFT

#define OV9655_REG_PSHFT 0x1B

◆ OV9655_REG_RAVE

#define OV9655_REG_RAVE 0x08

◆ OV9655_REG_RBIAS

#define OV9655_REG_RBIAS 0x2C

◆ OV9655_REG_RED

#define OV9655_REG_RED 0x02

◆ OV9655_REG_REFA8

#define OV9655_REG_REFA8 0xA8

◆ OV9655_REG_REFA9

#define OV9655_REG_REFA9 0xA9

◆ OV9655_REG_REG16

#define OV9655_REG_REG16 0x16

◆ OV9655_REG_RLMT

#define OV9655_REG_RLMT 0x60

◆ OV9655_REG_ROS

#define OV9655_REG_ROS 0x23

◆ OV9655_REG_SLOP

#define OV9655_REG_SLOP 0x7A

◆ OV9655_REG_TSLB

#define OV9655_REG_TSLB 0x3A

◆ OV9655_REG_VARO

#define OV9655_REG_VARO 0x69

◆ OV9655_REG_VER

#define OV9655_REG_VER 0x0B

◆ OV9655_REG_VPT

#define OV9655_REG_VPT 0x26

◆ OV9655_REG_VREF

#define OV9655_REG_VREF 0x03

◆ OV9655_REG_VSTART

#define OV9655_REG_VSTART 0x19

◆ OV9655_REG_VSTOP

#define OV9655_REG_VSTOP 0x1A

◆ OV9655_REG_VZST

#define OV9655_REG_VZST 0xA7

◆ OV9655_REG_XINDX

#define OV9655_REG_XINDX 0x74

◆ OV9655_REG_YAVE

#define OV9655_REG_YAVE 0x2F

◆ OV9655_REG_YINDX

#define OV9655_REG_YINDX 0x75

◆ PCLK_DELAY_0

#define PCLK_DELAY_0 0x00

◆ PCLK_DELAY_2

#define PCLK_DELAY_2 0x40

◆ PCLK_DELAY_4

#define PCLK_DELAY_4 0x80

◆ PCLK_DELAY_6

#define PCLK_DELAY_6 0xC0

◆ PCLK_OFF

#define PCLK_OFF 0x20

◆ PCLK_ON

#define PCLK_ON 0x00

◆ PCLK_POLARITY_REV

#define PCLK_POLARITY_REV 0x10

◆ PIN_REMAP_RESETB_EXPST

#define PIN_REMAP_RESETB_EXPST 0x08

◆ RESET_ENDPOINT

#define RESET_ENDPOINT 0x04

◆ RESETb_REMAP_SLHS

#define RESETb_REMAP_SLHS 0x80

◆ RGB565_FORMAT

#define RGB565_FORMAT 0x00

◆ RGB_555

#define RGB_555 0x30

◆ RGB_565

#define RGB_565 0x10

◆ RGB_NORMAL

#define RGB_NORMAL 0x00

◆ RGB_OUTPUT_AVERAGE

#define RGB_OUTPUT_AVERAGE 0x04

◆ SCCB_REG_RESET

#define SCCB_REG_RESET 0x80

◆ SINGLE_FRAME

#define SINGLE_FRAME 0x01

◆ SLAM_MODE_ENABLE

#define SLAM_MODE_ENABLE 0x40

◆ SOFT_SLEEP_MODE

#define SOFT_SLEEP_MODE 0x10

◆ UV_FIXED

#define UV_FIXED 0x10

◆ UV_NORMAL

#define UV_NORMAL 0x00

◆ VSYNC_NEG

#define VSYNC_NEG 0x02

◆ YUV_SEQ_UYVY

#define YUV_SEQ_UYVY 0x06

◆ YUV_SEQ_VYUY

#define YUV_SEQ_VYUY 0x04

◆ YUV_SEQ_YUYV

#define YUV_SEQ_YUYV 0x00

◆ YUV_SEQ_YVYU

#define YUV_SEQ_YVYU 0x02

Macros